Choose reference planes first. Then fit the dielectric construction to impedance, resin fill and mechanical requirements.
Compare three layer-allocation strategies
| Layer | Ground-rich routing | Dual power planes | Routing-dense concept |
|---|---|---|---|
| L1 | Signal | Signal | Signal |
| L2 | Ground | Ground | Ground |
| L3 | Signal | Signal | Signal |
| L4 | Ground | Power | Signal |
| L5 | Power | Power | Signal |
| L6 | Signal | Signal | Signal |
| L7 | Ground | Ground | Ground |
| L8 | Signal | Signal | Signal |
Ground-rich: start with return paths
Four signal layers and three ground layers make reference planning explicit. L3 can reference L2 or L4 depending on spacing. L6 sits between power and ground; decide the intended reference before calculating geometry.
Dual power: inspect every split
Two power layers can help distribute rails, but a split power plane is not a continuous reference. Avoid treating any adjacent copper shape as a suitable return plane merely because it is named “power.”
Routing-dense: budget for coupling
Six signal layers place adjacent inner signals without a dedicated separating plane. Broadside coupling and return paths require additional analysis. Layer count alone does not make this construction suitable for high-speed interfaces.
Layer changes: follow the return current
When a signal via changes its reference, evaluate the return-current transition. A ground stitching via helps when both references are ground; transitions involving power require a different return-path assessment.
Three arithmetic examples—not production-approved stackups
These symmetric foil constructions use four PP gaps and three dielectric-only cores. All eight copper layers are 0.035 mm; mask is 0.020 mm per side. Core dimensions are illustrative design inputs, not an availability list.
| Construction | Outer PP × 2 | Inner PP × 2 | Three cores | Copper + mask | Calculated total |
|---|---|---|---|---|---|
| Thin concept | 1 × 0.076 mm each | 1 × 0.130 mm each | 0.100 / 0.168 / 0.100 mm | 0.320 mm | 1.100 mm |
| General planning example | 1 × 0.076 mm each | 2 × 0.130 mm each | 0.203 / 0.203 / 0.203 mm | 0.320 mm | 1.601 mm |
| Thicker mechanical example | 1 × 0.076 mm each | 2 × 0.185 mm each | 0.254 / 0.280 / 0.254 mm | 0.320 mm | 2.000 mm |
The 1.601 mm example is a sum, not a promise that a press cycle delivers 1.601 mm. Resin fill, actual copper coverage and material tolerances change the finished result. The outer dielectric remains 0.076 mm in all three examples, so changing the board’s overall thickness does not by itself change the outer trace-to-plane height.
Approve the construction before detailed routing
- Ask for dielectric thickness after pressing, not just glass style or uncured sheet thickness.
- Review mechanical symmetry and copper distribution independently. Equal dielectric spacing does not guarantee balanced copper.
- Confirm Dk data appropriate to the material construction, frequency and solver method.
- Review the trace width and spacing against actual etching, plating and registration limits.
- Include stackup revision, material substitution rules and impedance coupons in the release package.
Source context: material construction data and TI high-speed layout guidance. Change these assumptions in the designer →