8-Layer Stackup Configuration
Layer Assignment
Configure each layer's function for optimal signal integrity and EMI control.
Stackup Summary
Standard 8-layer stackup is ideal for complex digital designs. Consider high-speed stackup for DDR4/DDR5 or high-frequency applications requiring controlled impedance.
Export Stackup
Microstrip Impedance
Common Impedance Targets
| Interface | Single-Ended | Differential |
|---|---|---|
| USB 2.0 | — | 90Ω ±10% |
| USB 3.0/3.1 | — | 90Ω ±10% |
| HDMI | — | 100Ω ±10% |
| PCIe | — | 85Ω ±15% |
| DDR4 | 40Ω | 80Ω |
| DDR5 | 40Ω | 80Ω |
| Ethernet (RGMII) | 50Ω | 100Ω |
| SATA | — | 100Ω ±10% |
Differential Pair Calculator
Standard 8-Layer Specifications
| Parameter | Standard | Advanced |
|---|---|---|
| Min. Trace Width | 4 mil (0.1mm) | 3 mil (0.075mm) |
| Min. Trace Spacing | 4 mil (0.1mm) | 3 mil (0.075mm) |
| Min. Via Drill | 0.2mm (8mil) | 0.15mm (6mil) |
| Min. Via Pad | 0.45mm | 0.35mm |
| Min. Annular Ring | 0.125mm | 0.1mm |
| PTH Aspect Ratio | 8:1 | 10:1 |
| Board Thickness | 0.8-3.2mm | 0.4-4.0mm |
| Impedance Tolerance | ±10% | ±5% |
Lead Times
| Service | Time | Premium |
|---|---|---|
| Prototype (1-5 pcs) | 7-10 days | +30% |
| Express Prototype | 5-7 days | +50% |
| Rush Prototype | 3-5 days | +100% |
| Small Batch (6-50 pcs) | 10-15 days | Standard |
| Production (50+ pcs) | 15-20 days | Standard |
All 8-layer PCBs include AOI inspection, electrical testing, and impedance verification at no extra cost. IPC Class 2 standard by default, Class 3 available on request.
Surface Finish Options
PCB Specifications
Cost Breakdown
Consider using standard 6/6 mil trace/space to reduce tooling costs. OSP surface finish can save 20% compared to ENIG while maintaining good solderability for most applications.
Via Parameters
Via Analysis
✓ Manufacturable - Via specifications are within standard 8-layer manufacturing capabilities. Aspect ratio is optimal for reliable plating.
| Via Type | Min Drill | Max Aspect |
|---|---|---|
| Through-Hole | 0.15mm | 10:1 |
| Blind Via | 0.1mm | 1:1 |
| Buried Via | 0.1mm | 8:1 |
| Microvia (HDI) | 0.075mm | 0.75:1 |
Laminate Material Selection
Material Comparison
| Property | FR-4 | High-Tg | Low-Loss |
|---|---|---|---|
| Dk (1GHz) | 4.3 | 4.2 | 3.4-3.7 |
| Df (1GHz) | 0.025 | 0.020 | 0.004 |
| Tg (°C) | 130-140 | 170-180 | 185+ |
| CTE-Z | 50 ppm | 45 ppm | 40 ppm |
| Max Frequency | ~1GHz | ~3GHz | 25GHz+ |
| Relative Cost | 1x | 1.3x | 3-5x |
Material Selection Guide
-
Standard FR-4: Digital designs <1GHz, cost-sensitive projects, general-purpose applications
-
High-Tg FR-4: Lead-free assembly, automotive, industrial, multiple reflow cycles
-
Low-Loss Materials: High-speed serial >10Gbps, RF/microwave, 5G, data center switches
-
Mixed Stackup: Use low-loss for critical signal layers, FR-4 for power planes to optimize cost
Optimize Layer Assignment
Route high-speed signals on layers adjacent to ground planes for optimal return path. Keep power and ground planes in the center for better EMI shielding.
Controlled Impedance
Always specify impedance requirements in fabrication notes. Include target values, tolerance, and test coupon locations. Use impedance calculators to verify trace widths.
Via Strategy
Use blind/buried vias strategically to increase routing density. Place stitching vias around high-speed signals. Consider via-in-pad with filled vias for BGA routing.
EMI/EMC Design
Maintain continuous ground planes under all high-speed traces. Use 20H rule for plane setback. Add ground stitching vias along board edges for shielding.
Power Integrity
Use solid power planes with minimal splits. Place decoupling capacitors close to IC power pins. Consider embedded capacitance for high-frequency decoupling.
Cost Optimization
Use standard 1.6mm thickness when possible. Avoid blind/buried vias unless necessary. Consider panelization for small boards to reduce per-piece cost.
Symmetric Stackup
Always use symmetric stackup construction to prevent warpage. Mirror copper distribution across the board center. Balance prepreg and core thicknesses.
Signal Integrity
Match trace lengths for differential pairs and parallel buses. Use serpentine routing carefully - minimize coupling. Keep return paths continuous and close to signals.
DFM Guidelines
Maintain minimum annular ring requirements. Use teardrops for via-to-trace connections. Keep copper-to-edge clearance ≥0.25mm. Include clear layer markings in silkscreen.
8-Layer PCB Design Resources
Design Rule Check
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Minimum trace width/spacing: Verified 4/4 mil minimum for inner layers, 5/5 mil for outer layers
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Via specifications: Drill size, pad size, and annular ring meet manufacturer requirements
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Copper-to-edge clearance: Minimum 0.25mm (10mil) maintained on all layers
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Solder mask clearance: Appropriate expansion set for all pad types
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Silkscreen clearance: No overlap with exposed pads, minimum 0.15mm line width
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Drill file format: Excellon format with correct units and tool table
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Layer naming: Clear, consistent layer names matching fabrication drawing
Signal Integrity Check
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Impedance control: Trace widths calculated and specified for target impedance
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Length matching: Differential pairs and buses properly length-matched
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Return path continuity: Ground reference maintained under all high-speed signals
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Crosstalk: Adequate spacing between parallel traces, 3W rule applied
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Via stitching: Ground vias placed appropriately for plane transitions
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Decoupling: Capacitors placed close to IC power pins with short return paths
Required Output Files for Manufacturing
| File Type | Layer | Extension |
|---|---|---|
| Top Copper | Layer 1 | .GTL |
| Inner Layer 1 | Layer 2 (GND) | .G2 |
| Inner Layer 2 | Layer 3 (Signal) | .G3 |
| Inner Layer 3 | Layer 4 (Power) | .G4 |
| Inner Layer 4 | Layer 5 (GND) | .G5 |
| Inner Layer 5 | Layer 6 (Signal) | .G6 |
| Inner Layer 6 | Layer 7 (Power) | .G7 |
| Bottom Copper | Layer 8 | .GBL |
| Top Solder Mask | — | .GTS |
| Bottom Solder Mask | — | .GBS |
| Top Silkscreen | — | .GTO |
| Bottom Silkscreen | — | .GBO |
| Board Outline | — | .GKO |
| NC Drill | — | .DRL / .XLN |