A 50 Ω requirement does not determine one universal trace width for an eight-layer PCB. A useful starting width depends on trace-to-reference distance, dielectric permittivity, copper thickness and the transmission-line structure. A fabrication-ready requirement also identifies the tolerance and how the result will be tested.
Identify the structure before choosing a formula
A surface microstrip has a signal trace on the outside of the board, dielectric below it and a reference plane underneath. A stripline sits between reference planes inside the dielectric. Coplanar structures add nearby conductors beside the trace. These structures have different field distributions; entering an inner-layer trace into a surface-microstrip formula does not make it an inner-layer solution.
The site calculator models a single-ended surface microstrip over one continuous plane. It uses a quasi-static Hammerstad–Jensen model with conductor-thickness correction. Its role is to check an initial geometry and show sensitivities, not to certify impedance. A solder mask coating, rough copper, etch shape and frequency-dependent material behavior are outside its model.
Build the input worksheet
| Input | Definition | Common mistake |
|---|---|---|
| W | Finished trace width | Using artwork width before etch compensation. |
| H | Dielectric distance from trace underside to plane surface | Using total board thickness or copper center-to-center distance. |
| T | Finished copper thickness | Using starting foil for a plated outer layer. |
| Dk | Permittivity consistent with construction and modeling method | Using one FR-4 number for every resin content and frequency. |
| Target and tolerance | Required single-ended impedance and acceptance band | Treating a nominal target as a full test specification. |
Run a controlled sensitivity experiment
Start with H = 0.100 mm, T = 0.035 mm and Dk = 3.90. Select a 50 Ω target and use the calculator’s width synthesis. Record the returned width and model assumptions. Then vary only the width by ±0.010 mm and observe the resulting impedance interval. Wider traces generally lower the calculated impedance for the same microstrip construction.
This experiment isolates one source of variation. It does not combine dielectric thickness tolerance, Dk uncertainty, plating variation and etching into a worst-case manufacturing budget. A complete sensitivity study must vary the other dimensions and material inputs too, using realistic bounds and correlations supplied by the process owner.
Do not turn two 50 Ω lines into an assumed 100 Ω pair
Differential impedance depends on the pair’s coupled fields. Trace spacing, reference distance and nearby copper affect coupling. Two isolated single-ended calculations are not enough to establish the odd-mode impedance of a routed pair. Use a coupled-line solver for differential microstrip or stripline, with the actual pair geometry and reference planes.
The same caution applies when a route approaches a plane edge or crosses a split. A uniform transmission-line formula assumes the reference exists continuously along the modeled line. A discontinuity requires layout review and possibly a field or circuit simulation. A calculator cannot infer the quality of the return path from a layer number.
Translate the design into a testable fabrication requirement
Specify which net class requires impedance control, the signal layer, reference plane, target and tolerance. Include differential pair spacing where applicable. Ask the fabricator to propose its production construction and adjusted geometry, then approve that proposal against routing clearances and interface constraints.
- Identify whether the geometry may be adjusted and who approves changes.
- Agree coupon structure, test method and the report to be supplied.
- Keep impedance coupon geometry representative of the production construction.
- Record material substitutions and require re-analysis when their electrical properties differ.
- Review connectors, vias and transitions separately from the uniform trace calculation.
What to retain at release
Keep the approved stackup, net-class impedance table, final geometry and test requirements together under one design revision. Retain the calculator result only as a planning record. The production agreement and test evidence establish what was built and accepted.
Continue with the impedance calculator or the manufacturing specification checklist. Model reference: Qucs microstrip technical documentation. Layout context: Texas Instruments high-speed PCB layout guidance.